An electronic image sensor captures images using light-sensitive photodetectors that convert incident light into electrical signals. Image sensors are generally classified as either front-illuminated image sensors or back-illuminated image sensors. As the image sensor industry migrates to smaller and smaller pixel designs to increase resolution and reduce costs, the benefits of back-illumination become clearer. In front-illuminated image sensors, the electrical control lines or conductors are positioned between the photodetectors and the light-receiving side of the image sensor. The consequence of this positioning is the electrical conductors block part of the light that should be received by the photodetectors, resulting in poor quantum efficiency (QE) performance, especially for small pixels. For back-illuminated image sensors, the electrical control lines or conductors are positioned opposite the light-receiving side of the sensor and do not reduce QE performance.
Back-illuminated image sensors therefore solve the QE performance challenge of small pixel designs. But small pixel designs still have two other performance issues. First, small pixel designs suffer from low photodetector (PD) charge capacity. This is because the first order charge capacity scales along with the area of the photodetector. Second, the process of fabricating a back-illuminated sensor consists of bonding a device wafer to an interposer wafer and then thinning the device wafer. This process produces grid distortions. These grid distortions lead to the misalignments of the color filter array, which increases the amount of pixel-to-pixel color crosstalk.
FIGS. 1(a)-(d) illustrates a method for fabricating a back-illuminated sensor in accordance with the prior art. FIGS. 1(a)-(d) depict a standard Complementary Metal Oxide Semiconductor (CMOS) wafer 100 that includes epitaxial layer 102 disposed on substrate 104. Together, epitaxial layer 102 and substrate 104 form device wafer 106. Alternately, manufacturers can use a silicon-on-insulator (SOI) wafer because the buried insulating layer provides a natural etch stop for the back-thinning of device wafer 106. Regardless of starting material, grid distortion is an issue with the back thinning process.
FIG. 1(b) depicts a finished device wafer 106. Typically, multiple image sensors 108 are fabricated in epitaxial layer 102. FIG. 1(c) illustrates the positioning of an interposer wafer 112 just before bonding. A typical interposer wafer consists of a silicon layer 114 and an adhesive layer 116, such as a CMP silicon dioxide layer. The fabricated device wafer 106 is bonded to the interposer wafer 112, and substrate 104 and a portion of epitaxial layer 102 are removed by first grinding, then polishing, and finally etching the last ten to hundred microns of silicon.
FIG. 1(d) illustrates a finished wafer 118 and an exploded view of a back-illuminated image sensor 108 in accordance with the prior art. Stress accumulates in insulating layer 120 due to the deposition process, and due to the conductive interconnects 122. There are also stresses in the adhesive layers 116, 124. The thinning of device wafer 106 reduces the strength of epitaxial layer 102.
FIG. 2 is an exaggerate distortion pattern due to thinning and stress relaxation of epitaxial layer 102. The dashed line 200 represents the undistorted wafer map of back-illuminated image sensors, while the solid line 202 depicts a final distorted pattern. The distorted pattern 202 is a problem when fabricating color-filter array 126 (see FIG. 1(d)) on a back-thinned image sensor. Almost all lithography equipment measures the alignment mark locations of eight to twelve image sensors 108 on the finished wafer 118, and then performs a global alignment. With modern interferometry techniques, global alignment provides better than ten nanometers (nm) alignment tolerances over three hundred millimeters (mm). In other words, global alignment is superior to die-by-die alignment. Also, blading-off a photolithography mask and aligning the mask on a die-by-die basis slows equipment throughput, thereby increasing costs. For a back-thinned wafer, the uncertainty of a finished wafer 118 position due to distortion (also known as overlay) is typically fifty nm to two hundred nm. For small pixels, uncertainties of fifty to two hundred nm lead to significant color-filter array misalignment, resulting in significant color cross talk. These uncertainties must be compared with a front-illuminated sensor where the overlay is typically less than twenty nm.
Referring again to FIG. 1(d), the prior art back-illuminated image sensor illustrates how grid distortion can result in color crosstalk between pixels. The two-sided arrow 128 represents the misalignment of the frontside photodetectors 130a, 130b, 130c with respect to the backside color filter elements 132a, 132b, 132c of a color filter array (CFA) when the CFA is fabricated using global alignment. With a frontside photodetector configuration, the grid distortion can result in light 134 leaking into a target photodetector (e.g., photodetector 130b) from an adjacent misaligned filter element (e.g., 132a).